Integrated circuit devices, such as field-programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs), may include circuits or logic blocks that can be used to perform any of a variety of functions. For example, input-output circuitry may be used to interface with external circuitry. As signals need to be transmitted to different circuit elements or blocks in an integrated circuit (IC) device, clock circuitry may be included in most IC devices to provide clock signals that may be used to synchronize the different circuit elements in the IC device.
To ensure proper synchronization, a balanced clock structure is generally needed to minimize clock skew when the clock signals are transmitted from one block to another in the IC (e.g., from a clock source to an input-output block). Generally, multiple metal traces may be needed to route all the different clock signals with a balanced clock structure such as an H-tree clock structure.
Input-output blocks implementing a double data rate (DDR) interface, for instance, may require up to five different clock signals (e.g., a half-rate clock and four full-rate phase-shifted clocks). Accordingly, in order to route five different clock signals through a six-layer balanced clock tree, a total of thirty (5 clock signals×6 clock tree layers) metal traces may be needed. These metal traces may occupy valuable space/area in the IC device.
An unbalanced clock structure may require fewer metal traces. For instance, a fly-by clock structure may require as few as five metal traces to route five clocks. However, routing clock signals through unbalanced clock structures may potentially cause clock skew between different circuit elements or blocks on the IC device.